From RTEMSWiki
; This is the macraigor command file for the CSB350.
;
; NOTE: This was adapted from csb250.mac and reset.s,
; since the csb350.mac was not included in the uMon
; support package for CSB350
; 08/25/04 Bogdan Vacaliuc (bvacaliuc@ngit.com)
;
speed 2
reset
;
; Setup Clocks
word 0xB1900060 = 0x00000021 ;392Mhz CPU Clock
word 0xB190003c = 0x00000001 ;66Mhz System Bus Clock
word 0xB1900064 = 0x00000008 ;96Mhz AuxPLL Clock
word 0xB1900014 = 0x00000100 ;enable 32Khz clock
delay 10 ;delay 10msec
;
; Setup Static Bus Controller
word 0xB4001000 = 0x00000243 ;RCE0 CFG - E28F640 Bank 0, BE, 16-Bit, Type 3 (FLASH)
word 0xB4001008 = 0x11f83fe0 ;RCE0 ADD - 8MB @ 0x1f8000000
;
; Setup SDRAM Controller - 1 32Mbyte bank at SDCS0
delay 1 ;wait 1ms before setup
word 0xB4000000 = 0x00552229 ;SDCS0 config - 12 Row, 9 Col, 4 Bank, CL2
word 0xB400000c = 0x001003F8 ;SDCS0 address, 32MB at 0x00000000
word 0xB4000018 = 0x74000C30 ;Program refresh (disabled)
word 0xB400001C = 0x00000000 ;Precharge all banks
word 0xB4000020 = 0x00000000 ;Issue two auto refreshes
word 0xB4000020 = 0x00000000 ;Issue two auto refreshes
word 0xB4000018 = 0x76000C30 ;Enable refresh
word 0xB4000024 = 0x00000023 ;send MRS Command to device on SDCS0
delay 1 ;wait 1ms after setup
;
; Clear all interrupst (disable all)
word 0xB0400044 = 0xFFFFFFFF ;IC0_CTL0.clr
word 0xB040004C = 0xFFFFFFFF ;IC0_CTL1.clr
word 0xB0400054 = 0xFFFFFFFF ;IC0_CTL2.clr
word 0xB0400074 = 0xFFFFFFFF ;IC0_MASK.clr
word 0xB1800044 = 0xFFFFFFFF ;IC1_CTL0.clr
word 0xB180004C = 0xFFFFFFFF ;IC1_CTL1.clr
word 0xB1800054 = 0xFFFFFFFF ;IC1_CTL2.clr
word 0xB1800074 = 0xFFFFFFFF ;IC1_MASK.clr
;
;
status
;The path of the following download depends on the system on which
;the tools were installed...
;download U:/targets/csb350/monitor/CSB350_tst.elf
;pc 0xA0400000
;go
