ChipSat

From RTEMSWiki

Information obtained from http://www.ee.surrey.ac.uk/Personal/T.Vladimirova/Research/SummaryofActivities.htm. More information on ChipSat is available from:

• http://www.estec.esa.nl/microelectronics/core/chipsat_abstract.pdf
• http://klabs.org/richcontent/MAPLDCon03/presentations/d/d5vladimirovas.ppt

The VLSI Systems Research Group of the Surrey Space Centre (SSC) has a long-term research programme, codenamed ChipSat, which aims to apply advanced micro- and nano- technologies to small satellite design 1 . A specification of a system-on-a-chip (SoC) for small satellite data processing and control was developed. The goal is to implement an on-board data handling (OBDH) system of a small satellite on a single mixed-mode application specific integrated circuit (ASIC) chip. The specification of the SoC is based on requirements derived for future satellite missions of Surrey Satellite Technology Ltd. (SSTL) and therefore includes provisions for enhanced remote sensing and data gathering capabilities.

A single chip implementation of a simplified version of an on-board computer (OBC) is in a process of prototyping on a high-density programmable logic chip using soft intellectual property (IP) cores. The system-on-a-chip OBC (SoC-OBC) is modelled on a simplified version of an on-board computer designed by SSTL. The SoC-OBC is based on the LEON microprocessor IP core - a full featured 32-bit SPARC V8 compatible RISC core, developed by ESA. A number of peripheral IP cores were developed such as a floating-point mathematical co-processor, a DMA controller, an Ethernet controller, and an FSK modem. A downsized implementation of the SoC-OBC consisting of a microprocessor core, a CAN core and an EDAC core was successfully integrated on a XILINX Virtex FPGA. Work has started on the development of an image compression engine. The real-time operating system RTEMS was successfully configured with the LEON processor and tested with application and benchmark programs.