Xilinx IP core drivers for RTEMS- diff attached
Robert S. Grimes
rsg at alum.mit.edu
Tue Dec 5 21:02:39 CST 2006
Hi Keith, Pete, Greg, et. al.
This has finally bubbled up to the top for me, and I am finally getting back
to the task at hand - getting RTEMS up on Virtex-4 FX60.
> >> Keith wrote:
> >> I'm in favour of this being checked straight into a new xilinx or
> >> virtex 405 bsp...
> > Pete wrote:
> > I also vote for a separate BSP.
I agree - separate BSP. But, maybe I'm a bit off on a tangent here, but
there is another issue I've been thinking about over the past several
months. The V2/V4 really don't represent simple boards, in the BSP sense.
So starting a new BSP may not be sufficient for all users, unless we are
willing/able to define a "standard platform". For example, I personally
don't like the default naming for components that Xilinx EDK generates.
Another example, address generation may vary. Or maybe I'm looking at this
wrong, and what we really will need to do is define the constraints on the
EDK design, instead of the other way around? Seems a little odd, at first -
the BSP defining the "board", instead of the other way 'round, but is this
the way to go?
> The emac currently in the bsp is the soft core one. I have a definite
> requirement to implement a driver for the hard core one in the virtex
> 4fx. I plan to do this early next year, unless someone else gets there
If I have any luck, I just may beat you to it, Keith. I also do not like
paying all that money, just to ignore the built-in hard core! I've
currently got the TEMAC (hard core) working in scatter-gather DMA mode under
Ed Sutter's MicroMonitor; a bit of overkill, as his monitor pretty much
requires only polled operation, as a portable monitor probably should.
> From my glances through the specs, I plan to connect this through the
> alternate dcr bus to reduce contention on the plb. The hardcore emac
> appears to be configurable to support either. Anybody have a preference
> for either configuration?
I have used the plb_temac component, and have assumed I'll continue to do
so. However, I'm not really tied to it. In fact, I'm not sure I fully
understand something here. I had originally been using pretty much the
out-of-box demo for the FX12-based ML403 board, but noticed that the soft
core emac used up a large amount of FPGA resources (IIRC 35-40% ?). I
thought using the TEMAC would cut this way down, but the
plb_temac/hard_temac combination seems to take up almost as much, again
IIRC. (Sorry, I'm at home right now, and my computer at work just died
anyway, so the real numbers are not available as I write this.)
Anyway, as soon as I can get a replacement machine at work, I intend to
really get cracking on getting RTEMS running, with scatter-gather DMA
Ethernet, using the plb_temac/hard_temac combination, unless this discussion
leads me down another path. Right now, I have two ml403 boards available
for this, but I'll be moving it to our custom FX60 boards when they become
available. I've been using the Xilinx EDK tools for the last several
months, and have become rather comfortable with them (proficient is still
around the corner, I suppose); I've been monitoring RTEMS for probably 4-5
years now, but haven't got any further than running the "hello world" app,
so I'm definitely behind the curve there, compared to you guys. But I've
committed our project to using this setup, and I'm more than willing to
contribute whatever I can, and am open to direction from more experienced
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