[Bug 2003] Instruction cache problem in gen5200 bsps

bugzilla-daemon at rtems.org bugzilla-daemon at rtems.org
Thu Feb 2 02:00:22 CST 2012


https://www.rtems.org/bugzilla/show_bug.cgi?id=2003

--- Comment #6 from Sebastian Huber <sebastian.huber at embedded-brains.de> 2012-02-02 02:00:22 CST ---
(In reply to comment #5)
> Otherwise we are getting machine check exception interrupt.(Actually
> ibats are required because there are two independent caches, instruction and
> data caches) I am not talking about setting MSR_IR bit. This is the first step.
> According to e300 Power Architecture Core Family Reference Manual rev4 ICE bit
> should also be set in HID0 register. But if this is done without setting ibats,
> machine check exception occurs.

On the MPC5200B that we have here I don't experience this behaviour.  Where is
this described in the manual?

We can of course add the IBAT configuration to the BSP, but in the current
setting the instruction cache works also.

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