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RTEMS ISR question - management of the ET PSR-bit on ERC32



On 03/10/2011 06:03 PM, Matthew McBraida wrote:
> Hi,
>
> I have a question about interrupt handling with RTEMS/ERC32:
>
> I understand from TSC691E Users manual issue I, sections 3.7.17 / 3.8.5
> / 3.8.5.4 that: a trap causes the processor to clear ET; a synchronous
> trap when ET=0 results in an error condition that forces a reset; and
> that RETT automatically sets ET back to 1.
>
> Am I right to believe that the RTEMS generic ISR ?_ISR_Handler()? sets
> ET to 1 just before calling the user-trap-handler, and then clears it
> again just after it returns?
>
> I guess that the end result of all this is that normally for most of the
> processing time of a trap handler, a synch trap occurring will not
> result in a processor error...
>
> (I refer to the TSC691E Users manual instead of the TSC695F manual due
> to the far greater detail given in the former).
>

Right, traps are enabled before calling the user trap handler and 
redisabled again after it. I just had the 4.6.6 code available, but you 
can see this on lines 615 and 645, respectively. 
(cpukit/score/cpu/sparc/cpu_asm.S).

Aleix