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SMP Step #2
- Date: Wed, 9 Mar 2011 12:16:05 -0600
- From: Jennifer.Averett at OARcorp.com (Jennifer Averett)
- Subject: SMP Step #2
Suggested modifications and complaints revolving around the patch for
Bug number 1729 should have been resolved with the latest version of the
patch. If we have no more comments on this patch it wil be merged next week.
Details on the patch are (from the PR):
This patch contains the next step on the path to SMP support. It adds an
allocated array of the Per_CPU structures to support multiple cpus vs a single
instance of the structure which is still used if SMP support is disabled.
Configuration support was added to explicitly enable or disable SMP. But SMP
can only be enabled for the CPUs which will support it initially -- SPARC and
Stub BSP support for SMP was added which lets us treat a single CPU system as a
single core SMP from an RTEMS data structure standpoint. This lets us verify
that we can allocate a array of one per CPU structures, create one IDLE task,
The i386 and sparc bsps are modified to be able to run when configured as SMP
using the stub BSP support.
The NEXT patch adds "real" SMP BSP support for the pc386 and LEON3 BSPs. But
since there is not an SMP aware scheduler yet, it is only exercised by test
programs which verify we can bring cores 2-n out of reset and initialize them.
We have to have an SMP aware scheduler to have tasks scheduled on those cores.
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