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Caches on G2 PowerPC/network problem



On 15/12/2008, at 11:11 AM, Till Straumann wrote:

> In any case, if you find that you have to
> manage cache coherency in software then
> you probably must ensure
>
> a) that descriptors are cache-line aligned
> b) RX buffers are cache-line aligned.


There is a further complication to this on devices like the PPC405EX,  
where there is no cache-snooping and there are multiple 8-byte  
descriptors per 32-byte cache block. In this case there is the  
alarming possibility that the DMA could try to update another  
descriptor in the same cache block during the softwares invalidate- 
read-write-flush sequence used to update the descriptor tags. The  
recommended solution to this is to use the MMU to label the descriptor  
arrays non-cacheable, which is what I have done.

Setting up the MMU has other advantages; with a little work in  
linkcmds it can catch attempts to execute code outside the text area,  
attempts to read or write outside the defined RAM area, or attempts to  
write to readonly data. This helps quite a bit with debugging.


---
Wi not trei a holiday in Sweden this yer?

Michael Hamel
ADInstruments Ltd, Dunedin, NZ