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Re: Cogent 637 board

This issue is also a problem for the SPARC port, which does not allow miss-aligned access. In my opinion, the network stack has a bug here as it uses a pointer to structure without checking the pointer alignment. The whole problem would be solved by splitting that access to the IP address in the IP header into two 16-bit reads, rather than a 32-bit read. It would require to modify the IP stack, but all these issues would be solved once and for all. Maybe the access could be done through a #define which would be empty on targets supporting unaligned access.

An other solution (which is used in eCos) is to implement an
unaligned access trap handler. The trap handler emulates the
access using two 16-bit reads. The overhead should not be
that large as it is only the IP addresses in the IP header
which are miss-aligned.


Jay Monkman wrote:
Camilo Alejandro Arboleda wrote:

It works now. But I have a question: do we know for sure that m_data is
miss aligned? Shouldn't we test it first?

Yes, I know for sure. Actually it's not m_data that is misaligned.

When I allocate the mbuf and cluster, m_data is 4-byte aligned. The ethernet
packet gets copied into it, starting at the beginning of the buffer, so the
ethernet header is 4-byte aligned. Since the IP header immediately follows the
ethernet header and ethernet headers are 14 (or is it 18?) bytes long, the IP
header is not 4-byte aligned.

I was able to find this using a debugger - <shameless plug> an Abatron BDI-2000
</shameless plug>.

I still don't understand why it didn't happen in 4.6, though.