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Re: ppc multlibs and BSP removal was Re: powerpc altivec support

"Joel Sherrill <joel@OARcorp.com>" <joel.sherrill@OARcorp.com> writes:

> I know this is going to stir up some discussion BUT here goes nothing.
> Is there anyway that the PowerPC exception code can be general up to a
> certain point and then invoke a BSP specific routine to peek for other
> interrupts? The MIPS has a general handler code which does general
> register saving and then invokes a method provided by the CPU model or
> BSP to figure out the interrupt source.

I don't see anything that would prevent such an implementation on

There is a problem that common exception (including external interrupt)
management code is slightly CPU-dependent (cache management, maybe some
power saving features must be handled, etc.). This obviously could be
handled by putting asm macro calls at appropriate points in the
general-purpose code. Then each processor variant will provide its own
implementation of these macros (one can substitute preprocessor defines
for macros).

Overall, there is nothing unique about PowerPC but the way things are
currently implemented.