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Re: PowerPC question
Leon Pollak wrote, On 2/9/2005 3:43 AM:
On Tuesday 08 February 2005 22:00, Smith, Gene wrote:
This is not really directly related to rtems but since there seems to
be a lot of powerpc users here I thought I would ask.
My timer interrupt is implemented using the PIT at vector offset
0x1000. Should setting the MSR register to 0x21000 (EE bit off)
disable the timer interrupt? This is for ppc405gpr. For some reason I
still seem to see the timer interrupt when MSR is set to this or even
when set to 0.
I remember to have the similar problem some (a lot of) time ago. I
think you have fallen into the same catch...:-)
I tried to switch the interrupts OFF by setting the MSR[EE} to zero in
a task. The trick is that task switch causes the MSR value to be
restored to the value it was in other tasks. You may find the
discussion of this on the mail list about 2-3 years ago...
I still think that this is not 100% correct way, but, seems to me Ralf,
insisted that this is correct. I solved my problem by masking
undesirable interrupts in corresponding peripherals.
Hope this helps...
I went back and found the MSR discussions you mention. I think it is
saying that if I disable the MSR's EE bit while stepping through a given
task it prevents me from stepping into the timer interrupt (which
happens if I don't set EE to 0). However, if I "continue" in gdb and a
task switch occurs, MSR will be restored in the switched-to task with EE
probably on and the timer interrupt then occurs. That is probably what I
am seeing. I have often set EE off and think that is a permanent change
and then see it come back on by itself (after continuing to a bp). I
guess to globally (in all tasks) turn off the timer interrupt I need to
turn off the PIT timer itself, not just MSR's EE bit while in a task.