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ISR Argument Proposal Request



Eric Valette writes:
 > gregory.menke at gsfc.nasa.gov wrote:
 >  > On the R3000, the
 > > difference between an exception and an interrupt is very small and
 > > handling them all in one routine with one type of stack frame has some
 > > advantages.
 > 
 > On the other hand, this is false on many other processors as nowadays 
 > IRQ dispatch, masking, prioritizing is usually done by programmable 
 > interrupt controller. I would tend to agree that in general, raw 
 > execption handling and irq handling are quite similar but we are not 
 > talking about this here.
 > 
 > Another example : why would I like to store 255 void when I just have 
 > seven or fifteen different irqs. Why shoul I push a frame when it is 
 > used only by exception code and not irqs...

I think we're in violent agreement- I'm not advocating not fancying up
the interrupt/exception handling and trying to make it consistent
across as many bsp's as possible, nor am I advocating the mips
approach as being somehow better or particularly advantageous.  I will
say however, that it may well be desirable to allow some bsp's to
remain primitive if its appropriate/desirable given the architecture.

That said, the principal overhead in the mips int/exception handling
is in the stack frame setup/teardown, so I think integrating the mips
bsp's into whatever model ends up being used should be a clear win and
I'll be happy to work on it.

Gregm