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Possible optimization bug; m68332 target



--------

Testing the rtems-ss-20010525 snapshot for the efi332/m68332 target
has reviled what seems to be an optimization bug with the following
gcc version:

m68k-rtems-binutils-2.11-3.i386.rpm
rtems-base-binutils-2.11-3.i386.rpm
m68k-rtems-gcc-gcc2.95.2newlib1.9.0-2.i386.rpm
rtems-base-gcc-gcc2.95.2newlib1.9.0-2.i386.rpm


The error showed up while running sp09.

When check_dispatch_disable_level() (macro from tmacros.h) is compiled
with an arg of 0, evaluation with -O4 optimization within the "if ( &&
)" fails with an incorrect branch address at address 0x80e06 shown
below. A -O optimization compiles correctly at this location but fails
in the same macro with a similar problem elsewhere. It _seems_ to be
related to the "extern volatile" type in the expression... a temporary
hack that seems to avoid the problem is included below.

Code segments follow....

john gwynne



/==============================================
/   from tmacros.h
/==============================================
#define check_dispatch_disable_level( _expect ) \
  do { \
    extern volatile rtems_unsigned32 _Thread_Dispatch_disable_level; \
    if ( (_expect) != -1 && _Thread_Dispatch_disable_level != (_expect) ) { \
      printf( "\n_Thread_Dispatch_disable_level is (%d) not %d\n", \
              _Thread_Dispatch_disable_level, (_expect) ); \
      fflush(stdout); \
      exit( 1 ); \
    } \
  } while ( 0 ) 


/==============================================
/   code from -O4
/==============================================
0x80dfc <Screen1+2148>:	addql #8,%sp
0x80dfe <Screen1+2150>:	addql #8,%sp
0x80e00 <Screen1+2152>:	movel 0xa78b8 <_Thread_Dispatch_disable_level>,%d0
0x80e06 <Screen1+2158>:	beqw 0x850af <Screen9+1247> <==***** WRONG *****
0x80e0a <Screen1+2162>:	movel 0xa78b8 <_Thread_Dispatch_disable_level>,%sp at -
0x80e10 <Screen1+2168>:	pea 0x9bb52 <_rodata_start+434>
0x80e16 <Screen1+2174>:	jsr 0x95998 <printf>
0x80e1c <Screen1+2180>:	moveal 0xa2b02 <_impure_ptr>,%a0
0x80e22 <Screen1+2186>:	movel %a0@(8),%sp at -
0x80e26 <Screen1+2190>:	jsr 0x95574 <fflush>
0x80e2c <Screen1+2196>:	pea 0x1
0x80e30 <Screen1+2200>:	jsr 0x95450 <exit>
0x80e36 <Screen1+2206>:	moveq #4,%d0


/==============================================
/   code from -O1
/==============================================
0x80e42 <Screen1+2218>:	addql #8,%sp
0x80e44 <Screen1+2220>:	addql #8,%sp
0x80e46 <Screen1+2222>:	movel 0xa7918 <_Thread_Dispatch_disable_level>,%d0
0x80e4c <Screen1+2228>:	beqs 0x80e7c <Screen1+2276> <==***** correct ******
0x80e4e <Screen1+2230>:	clrl %sp at -
0x80e50 <Screen1+2232>:	movel 0xa7918 <_Thread_Dispatch_disable_level>,%sp at -
0x80e56 <Screen1+2238>:	pea 0x9bbb2 <_rodata_start+434>
0x80e5c <Screen1+2244>:	jsr 0x959f0 <printf>
0x80e62 <Screen1+2250>:	moveal 0xa2b62 <_impure_ptr>,%a0
0x80e68 <Screen1+2256>:	movel %a0@(8),%sp at -
0x80e6c <Screen1+2260>:	jsr 0x955cc <fflush>
0x80e72 <Screen1+2266>:	pea 0x1
0x80e76 <Screen1+2270>:	jsr 0x954a8 <exit>
0x80e7c <Screen1+2276>:	moveq #4,%d0


/==============================================================
/ check_dispatch_disable_level() hack that avoids the problem
/==============================================================
#define check_dispatch_disable_level( _expect ) \
  do { \
    extern volatile rtems_unsigned32 _Thread_Dispatch_disable_level; \
    volatile int a=_Thread_Dispatch_disable_level; \
    volatile int b=_expect; \
    if ( b != -1 && a != b ) { \
      printf( "\n_Thread_Dispatch_disable_level is (%d) not %d\n", \
              a, b ); \
      fflush(stdout); \
      exit( 1 ); \
    } \
  } while ( 0 ) 


---------------------------------------------------------
                                John S Gwynne, PhD.
Mission Research Corporation    Email: jgwynne at mrcday.com
3975 Research Blvd              Tel: (937) 429-9261 x166
Dayton Ohio 45430-2625          Fax: (937) 320-2562
---------------------------------------------------------