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Q about PowerPC new exception processing.
- Date: 29 Sep 2000 20:12:49 +0400
- From: osv at javad.ru (Sergei Organov)
- Subject: Q about PowerPC new exception processing.
Eric Valette <valette at crf.canon.fr> writes:
> Sergei Organov wrote:
> > Eric Valette <valette at crf.canon.fr> writes:
> > [...]
> > > > Do we need to switch back to usual method of stack allocation or fix comments
> > > > in the header?
> > >
> > > I would suggest no to switch back as interrupt stack may need to be
> > > initialized much more early than what is actually done in rtems...
> > I thought interrupts are enabled as a result of first context load. And stack
> > allocation was made before that. What for do we need interrupt stack even
> > earlier? Am I missing something?
> No this is correct but also quite limitative. In thory, interrupt could
> be needed very eraly in the process and this can be done provided the
> code executed do not call the executive. Stack allocation is this way.
OK. Got it.
> > What actually bothers me is the fact of initialization of interrupt stack from
> > __rtems_end variable. It seems to be more useful to have separate symbol,
> > let's say, __rtems_isr_stack (and maybe __rtems_isr_stack_size), that are to
> > be defined by linker. Having this I can put interrupt stack to whatever memory
> > region I like (e.g., internal RAM of MPC505). Does it sound reasonable?
> Perfect. Note that if you are going to use the new execption scheme for
> other procs, I already have the code for mbx860. I'm just finishing the
> implementation of the new interrupt model for the @#$%@#$% CPM/SIU
If I decide to do for MPC505, I'll refer to mbx860, thanks. Interrupts
handling should be much easier for 505 than for 8xx, I believe, so I even have
no idea how "new interrupt model" differs from "old one". Is it 8xx specific?
> > But the new code itself doesn't depend on the way SPRG1 is initialized,
> > isn't it?
> Unfortunately it does depend on SPRG1. See
> c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S. Note that it is just
> related to performance...
Sure, it does depend on SPRG1. I meant that if we initialize SPRG1 by another
address (got from RTEMS core), the rest of code will continue to work. But as
you convinced me there are reasons to initialize interrupt stack without calls
to executive at early stages, then all this is irrelevant.