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CPU model for efi332

Yesterday, I wrote:

>     2738:       4afa 60fe       tas %pc@(8838 <.eb+0xa>)
>   This address appears to be in the Spurious_Isr function.

Chris Johns replied:

> This is the `halt' (0x4afa) instruction which is not decoded correctly
> by objdump.

  I determined this independently after I sent the initial message.
Since I don't have background mode enabled, I get an illegal instruction
exception.  Properly disassembled, that would read:

     2738:       4afa            bgnd
     273a:       60fe            bra 0x273a

> I am not sure if the `MC68331' has a BDM module but if it does and you
> enable it you will halt at this point.

  It does have BDM, and I don't enable background mode.  No BDM hardware
on the outside, although I did bring the signals to the recommended

> I suspect things are failing correctly :). It sort of looks like you are
> getting a spurious interrupt.

  Any ideas as to why?  The only interrupts which should be enabled are
the CTS input from the serial port and the SIM periodic interrupt timer.
Both are under control of code which is part of efi332.  I'll recheck
my hardware to see if there's any chance I'm getting an interrupt
through the IRQ inputs, and check over the initialization code again.
Any other thoughts?


					-- Mike Collins --